1. Field of the Invention
The present invention relates to a decoder circuit for selecting an analog voltage such as an analog grayscale voltage for a liquid crystal display.
2. Description of the Related Art
A thin-film-transistor (TFT) liquid crystal display generally includes a microelectronic chip, sometimes referred to as a source driver chip, that receives and decodes an m-bit input signal in order to select and output one of 2m positive and 2m negative analog grayscale voltages. The output voltage is supplied to the source electrodes of transistors in the display.
FIGS. 1 and 2 show examples of conventional decoder circuits used for output of positive voltages in a source driver chip. These circuits comprise p-channel metal-oxide-semiconductor (PMOS) transistors formed in an n-type well or n-well 10 biased at the positive power supply potential (VDD). The analog grayscale voltages are generated by a resistor ladder (not shown). Although typical values of m are six to ten, enabling the circuit to select from sixty-four (26) to one thousand twenty-four (210) analog voltage levels, circuits with four-bit and eight-bit input are shown for simplicity.
FIG. 1 shows a four-bit decoder circuit that selects and outputs one of sixteen analog grayscale voltages according to the combination of four input bit signals. Inverters 10, 11, 12, 13 invert the input signals: inverter 10 is coupled between an input node G0 and an output node G0B, inverter 11 is coupled between an input node G1 and an output node G1B, inverter 12 is coupled between an input node G2 and an output node G2B, and inverter 13 is coupled between an input node G3 and an output node G3B.
Nodes VH0 to VH15, which receive the sixteen analog grayscale voltages, are connected to the source electrodes of PMOS transistors P0_0 to P0_15. The gate electrodes of the even-numbered transistors P0_0, P0_2, P0_4, P0_6, P0_8, P0_10, P0_12, P0_14 are connected to node G0. The gate electrodes of the odd-numbered PMOS transistors P0_1, P0_3, P0_5, P0_7, P0_9, P0_11, P0_13, P0_15 are connected to node G0B.
A node Net1_0 is connected to the drain electrodes of transistors P0_0, P0_1 and the source electrode of transistor P1_0. A node Net1_1 is connected to the drain electrodes of transistors P0_2, P0_3 and the source electrode of transistor P1_1. A node Net1_2 is connected to the drain electrodes of transistors P0_4, P0_5 and the source electrode of transistor P1_2. A node Net1_3 is connected to the drain electrodes of transistors P0_6, P0_7 and the source electrode of transistor P1_3. A node Net1_4 is connected to the drain electrodes of transistors P0_8, P0_9 and the source electrode of transistor P1_4. A node Net1_5 is connected to the drain electrodes of transistors P0_10, P0_11 and the source electrode of transistor P1_5. A node Net1_6 is connected to the drain electrodes of transistors P0_12, P0_13 and the source electrode of transistor P1_6. A node Net1_7 is connected to the drain electrodes of transistors P0_14, P0_15 and the source electrode of transistor P1_7.
Among transistors P1_0 to P1_7, the gate electrodes of the even-numbered transistors P1_0, P1_2, P1_4, P1_6 are connected to node G1 and the gate electrodes of the odd-numbered transistors P1_1, P1_3, P1_5, P1_7 are connected to node G1B. A node Net2_0 is connected to the drain electrodes of transistors P1_0, P1_1 and the source electrode of transistor P2_0. A node Net2_1 is connected to the drain electrodes of transistors P1_2, P1_3 and the source electrode of transistor P2_1. A node Net2_2 is connected to the drain electrodes of transistors P1_4, P1_5 and the source electrode of transistor P2_2. A node Net2_3 is connected to the drain electrodes of transistors P1_6, P1_7 and the source electrode of transistor P2_3. Among transistors P2_0 to P2_3, the gate electrodes of the even-numbered transistors P2_0, P2_2 are connected to node G2 and the gate electrodes of the odd-numbered PMOS transistors P2_1, P2_3 are connected to node G2B. A node Net3_0 is connected to the drain electrodes of transistors P2_0, P2_1 and the source electrode of transistor P3_0. A node Net3_1 is connected to the drain electrodes of transistors P2_2, P2_3 and the source electrode of transistor P3_1. The gate electrodes of transistor P3_0 and transistor P3_1 are connected to node G3 and node G3B, respectively. An output node OUT is connected to the drain electrodes of transistors P3_0, P3_1. The transistors are accordingly connected in a tree structure with the output node OUT as the root node.
The n-well 10 in which transistors P0_0 to P0_15, P1_0 to P1_7, P2_0 to P2_3, P3_0, and P3_1 are formed is connected at one or more points to a power supply node and held at a power supply potential VDD equal to or greater than the highest of the analog grayscale voltage levels at nodes VH0 to VH15.
In this circuit, the states of the output node OUT depend on the combinations of the logical states of nodes G0 to G3 as shown in FIG. 3. That is, one of the sixteen voltage levels at nodes VH0 to VH15 is selected and output to the output node OUT according to the combination of the states of nodes G0 to G3, which are indicated individually in FIG. 3 and also as a hexadecimal (HEX) input code. When nodes G0 to G3 are all at the low or ‘0’ logic level, for example, transistors P0_0, P1_0, P2_0, and P3_0 are all turned on, so that the voltage level at node VH0 is output to the output node OUT. The other voltage levels at nodes VH1 to VH15 do not propagate to the output node OUT because the gate electrode of at least one of the transistors on each of the paths from nodes VH1 to VH15 to the output node OUT is at the high or ‘1’ logic level and the relevant transistor is turned off.
FIG. 2 shows an eight-bit decoder circuit that selects and outputs one of two hundred fifty-six analog grayscale voltages (received at nodes VH0 to VH255) according to the states of eight input signals (received at nodes G0 to G7). The increased number of input signals and analog grayscale voltages and the resulting increased number of transistors cannot all be shown in the drawing, but the circuit configuration follows the same plan as in FIG. 1.
In the circuit shown in FIG. 2, the states of the output node OUT depend on the combination of the logical states of nodes G0 to G7 as shown in FIG. 4. For each combination, one of the two hundred fifty-six voltage levels at nodes VH0 to VH255 is selected and output at the output node OUT. When nodes G0 to G7 are all at the ‘0’ logic level (the input code is hexadecimal 00h), for example, transistors P0_0, P1_0, P2_0, P3_0, P4_0, P5_0, P6_0, P7_0 are all turned on and the voltage level at node VH0 is output to the output node OUT. The other voltage levels at nodes VH1 to VH255 do not propagate to the output node OUT because the gate electrode of at least one of the transistors on each path from nodes VH1 to VH255 to the output node OUT is at the ‘1’ logic level and the relevant transistor is turned off.
Further details of the circuits in FIGS. 1 and 2 can be found in Japanese Patent Application Publication No. 2000-183747, which discloses a resistor ladder for generating a plurality of grayscale voltages and a selection circuit for selecting one of the grayscale voltages output from the resistor ladder.
A problem with the above circuit configuration is that when the selected analog grayscale voltage is much lower than the substrate (n-well) voltage of the PMOS transistors, a comparatively long selection time becomes necessary, degrading the response speed of the circuit, and in some cases the expected analog grayscale voltage level is not obtained.
FIG. 5 is a graph illustrating current characteristics of a typical PMOS transistor. The horizontal axis indicates the gate-source voltage VGS, that is, the gate potential minus the source potential. The horizontal axis indicates the drain current IDS, that is, the current flowing from the source terminal to the drain terminal. The multiple curves correspond to different values of the substrate-source voltage VBS, which is the substrate potential minus the source potential. The arrow indicates the direction of increasing substrate-source voltage VBS. It can be seen that the drain current IDS decreases not only with increasing gate-source voltage VGS, but also with increasing substrate-source voltage VBS.
FIG. 6 is an exemplary graph illustrating the analog grayscale voltages corresponding to the eight-bit input codes in the eight-bit decoder circuit shown in FIG. 2. The two hundred fifty-six analog grayscale voltages are related as follows:VH255>VH254>VH253> . . . >VH2>VH1>VH0
Voltage VH255 is the highest level, closest to the power supply potential VDD, and voltage VH0 is the lowest level. When transistors P0_0 and P0_255 are selected, voltages are applied to their terminals as shown in FIGS. 7 and 8. In this case, if the gate-source voltages VGS of transistors P0_255 and P0_0 are denoted VGS_255 and VGS_0, respectively, and their substrate-source voltages VBS are denoted VBS_255 and VBS_0, these voltages are given by the following equations:VGS—255=0(ground level)−VH255=−VH255VBS—255=VDD−VH255VGS—0=0(ground level)−VH0=−VH0VBS—0=VDD−VH0
A source driver for driving a TFT liquid crystal typically has a positive analog grayscale voltage range from about (½)·VDD to VDD−0.2 volts. If voltages VH255 and VH0 are set to these values (VH255=VDD−0.2 and VH0=(½)·VDD), the above equations become:VGS—255=−VH255=0.2−VDDVBS—255=VDD−VH255=0.2VGS—0=−VH0=−(½)·VDDVBS—0=VDD−VH0=(½)·VDD
Under these conditions, if the operating point of transistor P0_255 is indicated by point A in FIG. 5, the operating point of transistor P0_0 is at point B. The drain current IDS at point B is significantly less than the drain current IDS at point A. That is, the current IDS that flows when analog grayscale voltage VH0 is selected is significantly less than the current IDS that flows when analog grayscale voltage VH255 is selected, and this difference shows up in the response times of these decoder circuit during the selection period.
When the two hundred fifty-six analog grayscale voltages decrease in sequence from VH255 to VH0 (VH255>VH254>VH253> . . . >VH2>VH1>VH0) as shown in FIG. 6, if the gate-source voltage VGS and substrate-source voltage VBS applied when transistors P0_255 to P0_0 are selected are denoted VGS_255 to VGS_0 and VBS_255 to VBS_0, respectively, these voltage are related as follows:VGS—255<VGS—254<VGS—253< . . . <VGS—2<VGS—1<VGS—0VBS—255<VBS—254<VBS—253< . . . <VBS—2<VBS—1<VBS—0
If the drain currents IDS of transistors P0_255 to P0_0 are denoted IDS_255 to IDS_0, then from the graph in FIG. 5, these currents are related as follows, illustrating one of the characteristics of a PMOS transistor:IDS—255>IDS—254>IDS—253> . . . >IDS—2>IDS—1>IDS—0
This indicates that the higher the analog grayscale voltage is, the larger the current becomes, and the lower the analog grayscale voltage is, the smaller the current becomes. The response time of a transistor decreases as the current flowing through it increases, so if the response times of transistors P0_255 to P0_0 are denoted T255A to T0A, they are related as follows:T255A<T254A<T253A< . . . <T2A<T1A<T0A
This indicates that the higher the analog grayscale voltage is, the shorter the response time becomes, and the lower the analog grayscale voltage is, the longer the response time becomes. FIG. 9 is a timing diagram illustrating the response at the output node OUT when analog grayscale voltages VH255 and VH127 are selected repeatedly in alternation. The analog grayscale voltages selected according to the input codes correspond to those shown in FIG. 4.
The notation TMAX in FIG. 9 indicates the maximum allowable response time. When the voltage at the output node OUT does not reach the selected analog grayscale voltage level within this time, a liquid crystal display fault such as a bright or dark line or an irregular color may appear.
From the relationship T255A<T254A<T253A< . . . <T2A<T1A<T0A, the response time at the output node OUT is the shortest when analog grayscale voltage VH255 is selected, and is longer when other analog grayscale voltages are selected. The output node OUT reaches voltage level VH255 quickly, and response time T255A is sufficiently shorter than TMAX that no display fault occurs.
When analog grayscale voltage VH127 is selected, the voltages VGS, VBS are given as follows:VGS=−VH127, VBS=VDD−VH127
Assuming from the grayscale voltage graph in FIG. 6 that the analog grayscale voltage VH127 is set such that VH127=(¾)·VDD, the above voltages VGS, VBS can be expressed as follows:VGS=−(¾)·VDD, VBS=(¼)·VDD
The current IDS in this case, which is given by point C in FIG. 5, is about half the current IDS that flows when analog grayscale voltage VH255 is selected. Therefore, the response time at the output node OUT is approximately doubled, but the output node OUT still reaches voltage level VH127 within a time not exceeding TMAX.
FIG. 10 is a timing diagram illustrating alternate selection of analog grayscale voltages VH255 and VH7 and the resulting response waveform at the output node OUT. Since the current IDS that flows when voltage VH7 is selected approaches the current at point B in FIG. 5, the response time T7A at the output node OUT becomes much longer than the response time T127A. The output node OUT now needs nearly the whole of time TMAX to reach voltage level VH7, but since the condition T7A<TMAX is still met, no display fault occurs.
FIG. 11 is a timing diagram illustrating alternate selection of the analog grayscale voltages VH255 and VH0 and the resulting response waveform at the output node OUT. Since the current IDS that flows when voltage VH0 is selected is given by point B in FIG. 5, it is very greatly decreased, and the response time T0A at the output node OUT becomes even longer than response time T7A, exceeding the allowable time TMAX. In this case, since the output node OUT fails to reach the selected analog grayscale voltage level VH0 within the necessary time, the liquid crystal display cannot display the expected color, which may cause display faults such as, for example, a bright or dark line or an irregular color. Furthermore, if the analog grayscale voltage range is widened and voltage level VH0 is further decreased, or if the VGS and VBS characteristics of the PMOS transistors are degraded, the operating point when voltage VH0 is selected may move from the point B to point D in FIG. 5. At point D the gate-source voltage VGS fails to exceed the PMOS transistor threshold voltage (VTH), so the current IDS falls to substantially zero.
FIG. 12 is a timing diagram illustrating the response waveform at the output node OUT when the transistors operate at point D in FIG. 5. When the selection is changed from voltage VH255 to voltage VH0, the output node OUT begins to approach voltage level VH0, but then the gate-source voltage VGS of transistor P0_0 crosses the PMOS transistor threshold voltage (VTH), so transistor P0_0 turns off before the output node OUT reaches voltage level VH0. Therefore, the output voltage level at the output node OUT cannot reach voltage level VH0 even after an indefinitely long time.
As described above, in the conventional circuit, the voltages VGS and VBS increase as the selected analog grayscale voltage decreases, which may lead to a great reduction in current flow through the transistors in the decoder circuit. Resulting problems are that the selected analog grayscale voltage cannot be output within the necessary time, and in some cases cannot be output at all.